1. Field of the Invention
The invention relates to integrated circuit technologies, and more particularly to a processor having a reconfigurable circuit, and the like.
2. Description of the Related Art
Recently, reconfigurable processors capable of changing their hardware operations depending on applications have been under development. Among the architectures for realizing reconfigurable processors are ones using digital signal processors (DSPs) and field programmable gate arrays (FPGAs).
With FPGAs (Field Programmable Gate Arrays), circuit configurations can be designed relatively freely by writing circuit data after the fabrication of the large-scale integration (LSI). FPGAs are used for designing dedicated hardware. An FPGA includes basic cells and programmable wiring resources for linking the basic cells. The basic cells each have a look-up table (LUT) for storing a truth table of the logic circuit, and a flip-flop for output. With FPGAs, intended logic operations can be realized by writing both the data to be stored into the LUTs and wiring data. LSIs designed by using FPGAs, however, have extremely large packaging areas and high costs as compared to when designed by using application specific ICs (ASICs). Then, there has been proposed a method in which an FPGA is dynamically reconfigured to reuse the circuit configuration (for example, see Japanese Patent Laid-Open Publication No. Hei 10-256383).
FPGAs are high in the design flexibility of the circuit configuration and thus have high versatility. Nevertheless, they must include a large number of switches and a control circuit for controlling on/off the switches in order to allow connections among all the basic cells. The control circuit thus inevitably increases the packaging area. Moreover, the connections among the basic cells tend to require a complicated wiring pattern with greater wiring lengths, even with a number of switches connected to each of the wires. Longer delays thus develop from this structure. On that account, FPGA-based LSIs often remain in prototyping and experimental uses, and are unsuitable for mass production in view of packaging efficiency, performance, cost, etc. In addition, FPGAs require that configuration information be transmitted to a number of basic cells of LUT type. It thus consumes considerable time to configure the circuits. Consequently, FPGAs are not suited to applications where circuit configuration need to be switched instantaneously.
To solve the foregoing problems, studies have recently been made of ALU arrays in which multifunction devices having basic arithmetic functions, called arithmetic logic units (ALUs), are arranged in a number of stages. ALU arrays require no horizontal wiring since the processing runs in one direction from top down. Incidentally, as with FPGAs, each single ALU may be connected with all the other ALUs. In this case, however, the capability of passing data to any of the ALUs requires enormous numbers of wires and connection switches, contributing to an increase in circuit scale.